1. Field of the Invention
The present invention relates to an apparatus for a semiconductor memory device and a method of making a semiconductor memory device using a Dynamic Random Access Memory (DRAM) construction of the stack memory cell type.
2. Description of the Related Art
Due to the recent high demand for large-capacity semiconductor memory devices, increasingly greater integration is being employed in the design of these types of devices. Currently, one of the most widely used of these devices is the DRAM. In particular, DRAMs lend themselves to being highly integrable.
The memory cells constituting a DRAM are classified to three types according to the number of MOS transistors that constitute a single memory cell: four-transistor type, three-transistor type and one-transistor type. The one-transistor type comprises only one MOS capacitor for storing a charge (i.e., a high or low voltage charge), and one MOS transistor for transferring a charge. Because of its simpler structure and easier miniaturization than the other two types, the one-transistor type memory cell is typically employed in DRAMs of a 4K-bit size or of a greater size.
To achieve a larger memory capacity with a smaller area, various methods of providing a three-dimensional capacitance structure for the one-transistor type memory cells have been proposed. One of these methods provides for a stack type memory cell.
The stack type memory cell has a polysilicon-based multi-layer structure on a semiconductor substrate, wherein a dielectric film (silicon oxide or silicon nitride) is formed between a lower capacitor electrode (capacitor electrode) and an upper capacitor electrode (opposite electrode). One way to provide for larger capacity memories is to increase the surface area of the polysilicon film forming the capacitor electrode. This can be done by either decreasing or increasing the thickness of the polysilicon film layer.
FIG. 9 is a cross-sectional view of a stack type memory cell fabricated using conventional techniques wherein a thin layer of polysilicon film is used to form the capacitor electrode.
In this example, an N channel MOS transistor is used as a charge-transfer transistor. A pair of n.sup.+ type diffusion layers 102 and 103 are formed on a p type semiconductor substrate 101 and serve as the source and drain regions of an N channel MOS transistor. A gate electrode (word line) 105 is formed of a first polysilicon film, between the diffusion layers 102 and 103 via an interlayer insulating film 104. A gate oxide film 113 is formed between the gate electrode 105 and the semiconductor substrate 101.
A second polysilicon film 106 is formed on the interlayer insulating film 104 and serves as the capacitor electrode. The polysilicon film 106 contacts the diffusion layer 102 at a contact portion (memory node contact) D. A third polysilicon film 108 forms the opposite electrode on the polysilicon film 106. A dielectric film 107 is placed between the polysilicon films 107 and 108. A field oxide film 109, serving as a device isolating region, is formed adjacent to the diffusion layer 102 on the semiconductor substrate 101. A word line 110 is formed on the field oxide film 109 and adjoins the word line 105. An insulating layer 111, provided on the interlayer insulating film 104 and the polysilicon film 108, is overlaid by a bit line 112 which contacts the diffusion layer 103.
The memory node contact D has an inverted quadrangular pyramid having a cavity at the center due to the placement of word lines 105, 110 and the interlayer insulating film 104 as described above. By forming a thin layer of polysilicon film 106 along the interlayer insulating film 104, the surface area of the dielectric film 107 increases. The area shared by the opposite electrode (polysilicon film 108) and the capacitor electrode (polysilicon film 106) also increases as does the surface area of the dielectric film 107 lining the cavity of the memory node contact D.
FIG. 10 is a cross-sectional view of a stack type memory cell that is fabricated by forming a thick polysilicon film 106 for use as the capacitor electrode. The same reference numerals as used in the stack type memory cell shown in FIG. 9 will be given to denote the identical elements in FIG. 10. Given this thick polysilicon film 106 in the stack type memory cell as shown in FIG. 10, the area of the side-wall region (portion A) around the polysilicon film 106 likewise increases. This in turn results in an increase in the surface area of the dielectric film 107 which allows for the possibility of an enhanced memory capacity.
To increase the surface area of the dielectric film 107 in the stack type memory cell shown in FIG. 9, the diameter of the memory node contact D must be increased. This construction, however, tends to make the voltage charge, held by the cell, unstable. The greater the diameter of the memory node contact D, the thinner the interlayer insulating film 104 (portion B) between the individual word lines 105 and 110 and the capacitor electrode (polysilicon film 106). This results in an electrode which is unable to accommodate high voltage levels.
In the stack type memory cell shown in FIG. 10, the diameter of the memory node contact D is not associated with the surface area of the dielectric film 107. It is therefore possible to make the interlayer insulating film 104 (portion B) between the word lines 105 and 110 and the capacitor electrode 106 sufficiently thick, so that high voltage levels may be accommodated.
In the stack type memory cell shown in FIG. 9, the dielectric film 107 has a shape formed along the contour of the memory node contact D. Regardless of how thin the polysilicon film 106 is formed, an increase in the surface area of the dielectric film 107 is limited if the shape of the memory node contact D remains fixed.
In the stack type memory cell shown in FIG. 10, however, the surface area of the dielectric film 107 can increase as long as the polysilicon film 106 is formed thick. It should be noted that if a thick polysilicon film 106 is formed, a step portion in the bit line 112 will also increase. This will, in turn, likely cause the bit line 112 to be cut at the contact portion (portion E) between the bit line 112 and the diffusion layer 103. Effectively, this establishes a limit to increasing the thickness of the polysilicon film 106. Nonetheless, the stack type memory cell shown in FIG. 10 has enjoyed more widespread use than the stack type memory cell shown in FIG. 9.
Recent trends in DRAM design and manufacture have led to the further miniaturization of the stack type memory cell. Unfortunately, use of the stack type memory cell, as shown in FIG. 10, entails a limit to the range with which the DRAM's memory capacity can be effectively increased. Therefore, there is an unmet demand to increase the surface area of the dielectric film 107 in order to enhance the DRAM's memory capacity without causing an increase in the area occupied by the DRAM's memory cell.